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IDF, Fall 2004: Silvervale to virtualise server processing

By Alun Williams - San Francisco

Posted on 8 Sep 2004 at 09:47

Silvervale is Intel's codename for the virtualisation of server processor technology, intended to enable the more flexible switching of processor resources depending on different task requirements. It should also - Intel asserts - provide a basis for better security and reliability.

Vanderpool virtualisation is promised for the desktop ready for the arrival of Longhorn, but Silvervale will be among the features appearing in forthcoming Xeon and Itanium server processes, according to Abhi Talwalkar, General Manager of Intel's Enterprise Platforms Group, delivering a keynote (pictured) devoted to server developments.

Any technical details about Silvervale seem as elusive as rocking horse droppings, but it was announced as part of an updated roadmap for Intel servers.

First of all, there are plans for two new Xeon MP systems, dubbed 'Cranford' and 'Potomac', which will be based on a 90nm process and are expected to appear in the first half of 2005. Cranford, a 'value-oriented' 4-way processor, will target the lower-end of the market. As well as incorporating the 64-bit extensions of EM64T and Enhanced SpeedStep technology, they will be supported by the 'Twin Castle' chipset that supports PCI Express and DDR2 memory.

As was highlighted in the IDF opening keynote, dual-core technology will be appearing with 'Montecito' for the Itanium 2 and 'Tulsa' for the Xeon MP. Following on from Montecito, however, will be 'Montvale', the first Itanium processor based on a 65nm process technology. For two-way servers and workstations, Intel is lining up 'Irwindale' to follow on from the recently introduced 3.6GHz Xeon processors. Irwindale is essentially Nocona, but as well as a faster clock speed, it will feature a larger 2MB of cache.

Finally, even further on an undated horizon, is 'Whitefield' - a multi-core Xeon MP, which will share a common architecture with 'Tukwila', its multi-core Itanium 2 processor counterpart.

Note the difference between dual- and multi-core processing. Once the technology has been proved with two processors sharing the same silicon, it will be scaled up to cover numerous processor cores sharing the same chip.

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