Intel Core 2 Duo, the technical lowdown

 

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Posted on 14 Jul 2006 at 10:24

Finally, a desktop chip based on Intel's amazingly low power and fast Core micro-architecture is here. Not only that, but it's based on a new Core 2 design, which takes the same principle of high performance with low power and extends it even further. The good news is that desktop Core 2 comes in the same LGA775 package as Pentium D and Pentium 4 parts, meaning many existing boards will support it as a drop-in replacement after a BIOS update.

The new models

The new range starts with the Core 2 E4200, a bottom-end part with only 2MB Level 2 cache, 800MHz FSB and a 1.6GHz clock speed, and rises to the Extreme Edition X6800, which boasts a 2.93GHz clock, the full 4MB Level 2 cache and a 1,066MHz FSB.

The top-end standard desktop part is the E6700, which shares the same specification as the Extreme Edition but runs at 2.66GHz. The Extreme Edition is markedly different to previous Intel chips bearing the name: whereas the previous model, the Pentium Extreme Edition 955, differed significantly from the Pentium D processors with its dual HyperThreading cores and larger cache, the X6800 really is simply a Core 2 with its clock multiplier unlocked.

This was verified by slowing it down to a 10x clock multiplier - giving a 2.66GHz clock speed - at which setting it achieved exactly the same benchmark score as the standard E6700. The ability to overclock the CPU isn't to be sniffed at though; using a stock Intel heatsink, the board happily went up to a speed of 3.2GHz for a benchmark score of 1.84, and the reported temperature didn't rise above 65C.

The performance enhancements

The biggest single contributor to the improved performance of Core 2 is 'wide dynamic execution'. 'Wide' refers to the fact that every stage of the instruction fetch, decode and execution system is wider than before, allowing it to cope with up to four standard instructions simultaneously.

Previous designs had a three-wide instruction engine. 'Dynamic' covers the sophisticated schemes the CPU uses to operate speculative and out-of-order execution and branch prediction. The system owes a lot to the old NetBurst architecture, but the very deep 31-instruction pipeline - which led to a severe performance hit on a branch misprediction as the pipeline had to be cleared and refilled - is down to a depth of 14.

The out-of-order execution engine has been given more depth, though: with deeper instruction buffers - 96 instructions rather than the 64 of Core - Core 2 is able to search further ahead to find 'in-flight' instructions it can execute in parallel to keep all four execution paths fully utilised.

Advanced smart cache

As with Core in notebooks, Core 2's Level 2 cache is shared between the two cores. This gives two benefits over standard per-core cache.

First, it avoids a situation where one core is idling while the other core is labouring along at full pelt but unable to access the spare cache. The ability for one core to use all the cache effectively gives you a single-core CPU with 4MB when the situation demands. It's interesting to note that the two cores don't arbitrate for cache allocation: they simply compete for it, grabbing as much as they need when they can, so long as it isn't being used by the other core. Intel says this has turned out to be more efficient and effective than a complex arbitration system.

A secondary benefit is that cache use is optimised, since if both cores need access to the same data it doesn't need to be loaded twice. The 'advanced' prefix, which has appeared since the system debuted on the Core, is due to a doubling in bandwidth for transfers between Level 1 and Level 2 cache.