IBM, AMD announce improved performance for 65nm processes

By Steve Malone

Posted on 7 Dec 2005 at 10:18

IBM and AMD claim that they have made large improvements in 65nm processes that are emerging as the foundation of the new generation of microprocessors.

The companies have combined a number of optimisation techniques to provide a manufacturing process that can both increase the performance of devices built on 65nm processes as well as cutting power consumption.

The development will come as a particular relief to AMD as it is currently well behind archrival Intel in migrating its product line to 65nm technology.

At the International Electron Devices Meeting in Washington, the companies announced that they have successfully combined embedded Silicon Germanium (e-SiGe) with Dual Stress Liner (DSL) and Stress Memorization technology (SMT) on Silicon-On-Insulator (SOI) wafers.

According to papers released by the two companies, these combined techniques result in a 40 per cent increase in transistor performance compared to similar chips produced without stress technology, while controlling power consumption and heat dissipation.

The new process technologies reduce interconnect delay through the use of lower dielectric constant (lower-K) insulators, which can improve overall product performance and lower power consumption. Of course, this means nothing if it cannot be translated in commercial production. However, IBM and AMD say that the new technologies have shown ability to be manufactured at the 65nm generation and scaleable for use in future generations.