Intel demos 65nm process

By Steve Malone

Posted on 25 Nov 2003 at 10:42

Chip giant has demonstrated its next generation 65 nm technology, which it plans to put into full production in 2005. The demonstration was on full working SRAM (Static Random Access Memory) chips. A nanometer is one billionth of a meter. Intel claims that the new process will enable it to double the number of transistors on a single chip.

The new 65 nm is built around strained silicon, which offers a higher drive current and increases the speed of the transistors. High-speed copper interconnects and a low-k dielectric material both increase signal speed and lowers power consumption.

The demonstration was of 4Mbit SRAMs with each cell constructed of six transistors. Intel says that 10 million of these transistors would fit in one square millimetre. SRAMs form the memory caches which are built into modern processors.

The 65nm designs were developed at Intel's 300 mm development fab (called D1D) in Hillsboro, Oregon. Intel says the process can reuse the 193 nm and 248 nm lithography equipment currently used on its 90 nm process. The company says it expects to start production volume of 300mm wafers in 2005.