Intel revisits 3D transistor design

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By Alun Williams

Posted on 16 Jun 2003 at 12:17

Intel is progressing with its research into 3D transistor design - dubbed triple-gate transistors, or 'tri-gates'. As ever, higher processor performance, with greater power efficiency, is the goal.

New details were revealed at the 2003 Symposia of VLSI Technology and Circuits in Japan last week, and Intel has announced that work is moving from research to the development phase.

'Our latest research indicates that the scalability, performance and excellent manufacturability of our tri-gate transistor makes it a strong contender for production as early as 2007 on our 45nm process technology,' said Sunlin Chou, general manager of Intel's Technology and Manufacturing Group. 'The results place non-planar, 3D transistor structures among the promising nanotechnology innovations that we will use to extend silicon scaling.'

According to the researchers, the 'triple-gated transistor design' raises the transistor above its silicon base - the traditional 'flat' transistors - allowing electronic signals to travel on top and along both vertical sidewalls. The analogy that Intel uses is that a one-lane road is turned into a three-lane highway, without using more space.

Transistors are the mini On-Off switches that are combined to build microprocessors.

Intel first unveiled its research in this area back in September 2002 - Intel's future is 3D. Since that time, Intel researchers have managed to shrink the size of the tri-gate transistor (measured by the gate length) from 60 nanometers down to 30. This enables them to switch on and off faster, which in turn should enable faster processors.

As we said at the time, no Intel story is complete without a reference to Moore's law - which states that chip capacity will double every couple of years - and this one's no different. The significance of the research is that it will help Intel fulfil this law, even as the industry hits the barriers of how it is physically possible to manipulate signals in silicon.

'Our research shows that below 30 nanometers, the basic physics of the flat, single-gate planar transistor leaks too much power to meet our future performance goals,' said Dr. Gerald Marcyk, director of the Components Research Lab at Intel. 'The tri-gate transistor design will allow Intel to build ultra-small transistors that achieve high performance with low power and continue driving the pace of Moore's Law.'