Web-on-chip research to push processor performance

 

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By Stewart Mitchell

Posted on 11 Apr 2012 at 09:34

Multicore processors could get a speed boost by borrowing from web networking ideas, according to scientists at the Massachusetts Institute of Technology.

Touted as a replacement for bus technology that can lead to bottlenecks, the researchers' ideas would mimic how routers send data round the web to speed data around processors.

“A typical chip might have six or eight cores, all communicating with each other over a single bundle of wires, called a bus,” the researchers said. “With a bus, however, only one pair of cores can talk at a time, which would be a serious limitation in chips with hundreds or even thousands of cores, which many electrical engineers envision as the future.”

The idea is to prevent traffic jams currently found in on-chip networks where data can get backed up when travelling between different cores.

“A packet of data traveling from one core to another has to stop at every router in between,” the researchers said. “Moreover, if two packets arrive at a router at the same time, one of them has to be stored in memory while the router handles the other.”

According to MIT electrical engineering professor Li-Shiuan Peh, the separate cores would be more efficient if they communicated by mimicking the packet transmission used by computers connected to the internet.

If two packets arrive at a router at the same time, one of them has to be stored in memory while the router handles the other

In Peh's model, each core would have its own router, which could send a packet down any of several paths, depending on the condition of the network.

The researchers said that although the number of cores talking to each other was currently manageable using bus technology because of low levels of cross core communication, the situation would change as more and more cores were added to processors.

“Buses have hit a limit,” Peh says. “They typically scale to about eight cores. The 10-core chips found in high-end servers frequently add a second bus, but that approach won’t work for chips with hundreds of cores.”

Bus lanes

The researchers have developed a test chip which they claimed showed the idea worked, and that it also made multicore processors more power efficient.

“Buses take up a lot of power, because they are trying to drive long wires to eight or 10 cores at the same time,” Peh said, adding that in her model, each core communicates only with the four cores nearest it. “Here, you’re driving short segments of wires, so that allows you to go lower in voltage.”