Intel measures up to a 90 nanometer chip-making process

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By Alun Williams

Posted on 13 Aug 2002 at 16:46

Advanced transistors, strained silicon, and high-speed copper are elements of Intel's next-generation 90 nanometer (nm) manufacturing process.

To put things in context, a nanometer is one-billionth of a metre, and the new process involves the use of gates one two-thousandth the width of human hair.

The 90nm process is regarded by Intel as the 'next generation' after the 0.13-micron process and will be the means to continue fulfilling Moore's law. Named after the co-founder and CEO of the chip giant, this was a prediction, made back in the mid-sixties, that chip data capacity would double every two years.

In a barely concealed dig at chip rivals AMD, the general manager of Intel's Technology and Manufacturing Group, Dr. Sunlin Chou, claimed: 'While some are slowly transitioning production to 130 nm (0.13 micron) process on 200 mm wafers, we are moving ahead with the most advanced 90 nm technology exclusively on 300 mm wafers. This combination will allow Intel to make better products and reduce manufacturing costs.'

One of the first commercial chips to be made on the process, by the second half of 2003, will be the processor codenamed Prescott, which is Intel's next-generation desktop processor.

Essentially, there are three important elements to the new process: higher-performance, lower-power transistors, strained silicon, and high-speed copper interconnects.

Featuring logic gates only 50nm in length, Intel claims them as the highest performing CMOS transistors in production (the advanced transistors in the Pentium 4 measure 60 nm). Thin is in, in this case, as the transistors feature gate oxides that are only five atomic layers thick and a thin gate oxide increases transistor speed, which helps build faster microprocessors.

Claiming it as the first process in the industry to implement strained silicon in production, this form of silicon allows current to flow more smoothly, which also increases the speed of transistors.

In terms of high-speed copper interconnects, the process involves a new carbon-doped oxide (CDO) dielectric material that increases signal speed inside the chip and reduces chip power consumption.

The system has been proved already when, back in February, Intel used its 90nm process to make the world's highest capacity SRAM chips at 52 megabits. These chips pack 330 million transistors into an area of 109 square millimetres, about the size of a fingernail.

'Intel's 90nm process is very healthy today and we are routinely producing these wafers and chips in our development fab,' said Mark Bohr, Intel Fellow and director of process architecture and integration. 'By next year, we will be the first company to have a 90nm process in volume manufacturing.'