Intel disappoints with Nehalem specifications

 

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Posted on 17 Mar 2008 at 17:19

Intel has firmed up the details of its next-generation Nehalem processor architecture which will replace the current Core 2 designs.

It will definitely be released before the end of this year, according to the company, but initial specifications look surprisingly tame.

The surprise is that the first Nehalem parts - likely to be consumer-level - will contain just four cores, as opposed to the six or eight that have been speculated. And these quad-core parts will contain only 9MB of cache in total, as opposed to the 12MB of current quad-core Core 2 Extreme Edition parts.

The odd cache complement is down to the brand new architecture which, in an ironic twist, bears a very strong resemblance to AMD's Barcelona chip designs. It introduces a third-level shared cache - 8MB in the as-yet unnamed launch part - and gives 256KB of dedicated level 2 to each core to arrive at the 9MB total.

In addition, it abandons the traditional front-side bus design Intel has doggedly clung to, and introduces a dedicated on-chip memory controller: the very same concept AMD pioneered when it launched the Athlon 64 processor back in 2003.

Although the first designs will be quad-core, Intel claims the design will scale from two cores all the way to eight, with scalability enhanced by a caching scheme known as an inclusive-cache policy. This guarantees that any data in the first and second levels of cache must also be present in the third level, giving every core easy access to all cache data.

Intel's Stephen L Smith claims the Nehalem design is "the most scalable design we've ever produced". He also calls it "the most dynamic," referring to its ability to adjust power consumption based on workload, although the details of how this has been achieved are still under wraps.

New chipset

The desktop versions of Nehalem will run on a new motherboard chipset, codenamed Tylersburg. It will feature a three-channel memory interface, using a new point-to-point link (much like AMD's HyperTransport) for what Intel calls "massive memory bandwidth", with up to three memory modules per channel. Nehalem/Tylersburg will be available in DDR3 variants only.

There are architectural enhancements including a new second-level branch prediction unit, but the basic design builds on the existing Core microarchitecture - it's not a ground-up design.

In the absence of bucketloads of Level 2 cache and with the same number of cores as current CPUs, the question on most people lips will be where the performance gains are going to come from over the current Penryn parts?

The most obvious answer is in higher clock speeds, but an Intel spokesman could tell us only that "we're not disclosing clock speeds at launch".

Author: David Fearon