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Giuseppe Amato, AMD's Technical Director for EMEA, was briefing journalists about developments, conveniently ahead of Intel's Beijing IDF, and it was Amato who first revealed details of the K10 architecture back in September 2006 - AMD outlines its quad-core computing.

There was the same emphasis on backward compatibility - the new chips will be Socket F (1207) compatible, requiring a BIOS update, and highlighting of integrated memory management, but what was new? Release dates were firmed up, more cache details were outlined, especially for the subsequent desktop release of the core, and more flexible power management features were highlighted.

Whereas Intel has been first to market with 'quad-core' Xeons and Core 2 Extreme chips, these involve a 'dual die' architecture (two separate dual-cores packaged together), whereas AMD has pursued a native design with four cores sharing the same silicon substrate.

Specifically, the native design, with three levels of cache - variously shared among the cores - and an integrated memory controller, is designed to avoid bottlenecks on the system bus (going out to, and back from, an external memory controller). This is an issue AMD is keen to highlight for the performance of equivalent Intel offerings.

Each of the four cores will have 64KB of Level 1 cache, followed by a larger 512KB block of Level 2 cache. Finally, there will be 2MB of shared Level 3 cache. This combination of data sharing can enable more efficient thread processing for applications, he claimed.

Amato also hinted at a more precise release date. The chip, based on 65nm process technology, has long been scheduled for '2H07', but he said today the chip would appear at the 'beginning of the second half' of the year - cueing up a July release. The desktop chip would appear would be at 'the end' of the year.

Talking of desktop releases, Amato would not officially confirm

On the mobile side, there will be changes to the basic core. AMD will be cutting out non-mobile specific logic to better improve power consumption and thus battery life, he stated.

Indeed power consumption was a recurring theme of the talk - performance per watt per dollar being an increasingly important metric, both for server-packed data centres and laptop battery life. Interestingly, Amato also highlighted the flexibility of power management in the new chips.

Specifically there is the ability to throttle back on the power of individual cores - the power will be independently adjusted, based on the individual working status of a core (as opposed to being locked to match the demands of whichever is the most intensively used core, which is the case for current AMD dual-core chips). There are also changes in logic design, for the cores to automatically shut down areas of logic when not in use, to reduce power consumption.

Talking of playing with individual cores, Amato coyly flagged the potential appeal of the chip for overclockers, with the ability to tweak the clock speeds of the separate cores, while stressing his official AMD stance that such tweaking would be at the owner's own risk.

More details of the equivalent desktop and mobile chips were promised for September.

Why is K10 the successor the K8 Rev F core? Amato explained that the transition from 90 to 65nm process technology implicitly represented a 'K9' and that rather than the use the engineering reference K8L (to signify lower power requirements), AMD marketeers chose to highlight the changes in the core, with the designation K10.

Back in December 2006 demonstrated (AMD goes native with quad-core demo 99333) its 'Barcelona' native quad-core x86 server processor at its annual AMD Industry Analyst Forum. The company had just unveiled the dual-CPU Quad FX platform, which comprises a pair of dual-core FX-70 parts and was AMD's response to the Intel Core 2 QX6700 Extreme CPUs.