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Opteron

Posted on 8 Feb 2008 at 12:14

In theory, testing the relative performance of Intel and AMD for enterprise-level applications should be simple. Server componentry tends to be standardised and use similar design. In practice, we weren't able to do so.

Our test servers came from Boston (www.boston.co.uk) in the form of two Supermicro 1U rack chassis: an 102IM-T2B quad-core Opteron-ready system, and a 6015B-TV for the Xeons. The two sport identical basic chassis designs, identical hard disks, identical power supplies and even identical CD-ROM drives; no problems there. When it does finally arrive, the quad-core Opteron server and workstation range is slated to be broader than the limited number of Phenom models. As with the dual-core Opteron range and Xeon, the range is split into dual-processor and multiprocessor (up to eight-way) ranges, dubbed the 2300 and 8300 series respectively. Initially there will be five 2300s in the range, with two low-power HE variants with a TDP (thermal design power) of 55W as opposed to the standard 75W. Clock speeds vary from 1.7GHz to 2GHz . The 8300 series will comprise four models including two HE versions, ranging from 1.8GHz to 2GHz, with the same 75W TDP for standard and 55W for HE versions.

The design of the quad-core Opteron itself is more or less identical to that of the Phenom, with the same three-tier cache arrangement of a fixed 512KB L2 and shared 2MB L3. The only significant difference is an extra HyperTransport link for processor-to-processor communication. AMD claims this is a particular boost for a server system: with a multiprocessor Xeon server, traffic between processors has to travel out onto the front side bus, which increases latency and sucks up bandwidth that could be better used for unhindered memory-to-CPU traffic. Bandwidth of the HyperTransport links is impressive, with 8GB/sec on each link making it very difficult to saturate the system.

As with Phenom, the memory support for quad-core Opteron is limited to the design and architecture of the CPU itself, with the directly integrated memory controller rather than an off-board MCH. But a final hardware difference between them is the type of memory supported. Although, like Phenom, you're forced to stick with DDR2, Opteron allows for ECC (error-checking and correction) RAM for better resistance against single-bit memory corruption. Maximum memory speed is 667MHz. Because of the direct connection between main memory and the CPU, the total RAM complement needs to be split between two banks, with half accessed by each processor. The Boston server is fitted with two banks of four slots, allowing for a maximum total of 32GB.

Our issues arose from the fact that despite quad-core Barcelona Opterons nominally having launched in September last year, there were still no processors available. AMD itself told us that it would love to send us some but simply couldn't get hold of samples. Calls to vendors met with a universal chorus explaining they hadn't received any stock from AMD.

The explanation for the bizarre state of affairs - a processor company being unable to provide samples of its own processor - came with an official announcement on 14 December 2007. At an AMD financial analyst summit, the company's chief executive Dirk Meyer admitted that the launch of Barcelona has been horribly botched, and revealed that a design error had meant production was temporarily stopped. The error in question is with the processor's TLB (translation lookaside buffer). A TLB is nothing new - all modern processors use them to perform address-map translation. Errors in chip designs are nothing new either, but this one has managed to stall a processor that was already plagued by production delays. The fix AMD has now implemented is based around a BIOS update, and the underlying issue won't be fully fixed until the next revision of the design, the B3 stepping.