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[PSUs]| Thursday 28th September 2006 |
While the base specification is nothing too startling, it's a marked step-up from the point of view of wireless networking capabilities, and there's a brand new aspect to the platform.
Unsurprisingly, the platform remains centred around a Core 2 Duo processor rather than a quad-core part, since power consumption of quad-core will remain too high until 45nm parts appear later next year.
The interesting stuff begins with the integration of the recently announced flash-memory accelerator module, known currently by its codename 'Robson'. This is a module designed to act as a fast, smart, non-volatile application cache memory, sitting between the RAM and hard disk subsystems.
The idea is that Robson will permanently cache commonly used files and allow faster application load times, faster resume from standby - Intel quotes a 2x performance benefit in both these areas - and a slight decrease in power consumption by reducing hard disk activity. Typical capacities for a Robson module will initially be 1GB - 8GB. The drawback is that it will only work with Windows Vista.
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On the wireless front, Santa Rosa will sport an 802.11n MIMO (multiple in, multiple out) radio module to replace the 802.11a/b/g adaptor in current Centrino Duo platforms. The module, codename Kedron, conforms to current draft-n specifications, providing two transmitters and three receivers for what promises to be exceptional mobile wireless performance.
WiMax was also pushed to centre stage, with support for the 802.16e (Mobile WiMax) standard on the cards in the medium term. There was even an announcement of an official partnership with Nokia to provide future 4G/HSPDA services that will be directly integrated into Santa Rosa and its derivatives.
Once Santa Rosa was out of the way, Perimutter moved on to a Microsoft love child that Intel appears now to be embracing: the UMPC (ultra-mobile PC). In a cryptically phrased few minutes of his keynote he promised a processor part consuming half the power and occupying a quarter of the current size next year, and a part consuming 10x less power in 2008. This wasn't referenced to anything in particular, making it hard to divine what he was actually getting at. When pressed in the Q&A session after his keynote all he would say is that these new wonder-parts would 'not be Core 2 Duo-based'. Apparently they'll be processors for UMPC use only, and it would be reasonable to assume they'll be single-core parts.
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